1. Field of the Invention
The invention relates to analog-to-digital converters (ADC), and more particularly to gain error calibration of ADCs.
2. Description of the Related Art
An analog-to-digital converter converts an analog input signal to a digital output signal. Analog-to-digital converters are classified into several categories including flash ADCs, pipelined ADCs, and cyclic ADCs. Among the three ADC categories, a flash ADC has the shortest latency, because it has the simplest circuit structure. A flash ADC comprises multiple comparators directly comparing an analog input signal with multiple reference voltages to generate a digital output signal. When the required resolution of a digital output signal increases, a flash ADC must include a great number of comparators, increasing circuit complexity and chip area thereof. Thus, a flash ADC is only used when resolution of the digital output signal is low.
Compared with a flash ADC, a pipelined ADC and a cyclic ADC require fewer comparators and occupy less chip area to generate a high resolution digital output signal. FIG. 1 is a block diagram of a conventional pipelined ADC 100. The pipelined ADC 100 comprises a plurality of stages 101˜10N connected in series, with each stage generating a few bits of the digital output signal Dout. In the series, a preceding stage generates a stage output value indicating more significant bits of the digital output signal Dout, and a subsequent stage generates its stage output value indicating less significant bits of the digital output signal Dout. For example, the first stage 101 generates a stage output value do1 indicating the most significant bits, and the second stage 102, a subsequent stage of the first stage 101, generates a stage output value do2 indicating less significant bits. If the ADC 100 comprises N stages 101˜10N, the stages 101˜10N sequentially generate stage output values do0, do2, . . . , doN, and the gain error correction module 120 then collects the stage output values do0, do2 . . . , doN to generate the digital output signal Dout. Because each stage only generates a few bits of the digital output signal Dout, the signal resolution of the stage output value is lower and each stage requires fewer comparators to operate.
After a preceding stage generates a stage output value thereof, the preceding stage subtracts the stage output value from its stage input signal to obtain a residual signal, and amplifies the residual signal according to a predetermined gain value to obtain a stage output signal as the stage input signal of a subsequent stage. For example, the stage output signal R1 of the first stage 101 is the stage input signal of the second stage 102, and the stage output signal R2 of the second stage 102 is the stage input signal of the third stage 103. However, the actual gain value of each stage often deviates from the predetermined gain value due to chip fabrication errors or rise in chip temperature. The difference between the actual gain value of a stage and the predetermined gain value is referred to as a gain error of a stage. A gain error makes a preceding stage generate a mis-amplified stage output signal, causing errors in the stage output values of all subsequent stages in the series. Thus, the gain error of a stage must be estimated to ensure accuracy of the digital output signal Dout.
FIG. 2 shows a conventional process for estimating a gain error of a first stage 201 of a pipelined ADC 200. To estimate the gain error deviating from the predetermined gain value of the first stage 201, a gain error correction module 220 first generates a correction number P1. The first stage 201 then processes the residual signal with the correction number P1 before the residual signal is amplified. FIG. 3 is a block diagram of the first stage 201 of the pipelined ADC 200 of FIG. 2. After the first stage 201 generates a stage output value do1, the first stage 201 subtracts both the stage output value do1 and the correction number P1 from the stage input signal Vin to generate a residual signal Z. An amplifier 312 of the first stage 201 then amplifies the residual signal Z to generate the stage output signal R1′. Because the residual signal Z is affected by the correction number P1, if the amplifier 312 has a gain error ε, the stage output signal R1′ is affected by both the correction number P1 and the gain error ε. Thus, the stage output values do2′, do3′ . . . , doN′ of all of the subsequent stages 202, 203, . . . , 20N are affected by both the correction number P1 and the gain error ε, and the gain error correction module 220 can determine the gain error ε by correlating the correction number P1 and the stage output values do2′, do3′, . . . doN′.
Two stages of a pipelined ADC can share a common operational amplifier to amplify the residual signals thereof. Additionally, because a plurality of stages of a cyclic ADC share a common physical circuit, the stages of a cyclic ADC also use a common operational amplifier to amplify the residual signals thereof. When multiple stages of a ADC share a common operational amplifier, because the operational amplifier has only one actual gain value, the gain error of the multiple stages are the same and require only one estimate. Thus, if the first stage 201 and the second stage 202 share a common operational amplifier to amplify the residual signals thereof, the gain error correction module 220 generates only one correction number P1 to estimate the gain error of either the first stage 201 or the second stage 202. After the gain error estimate is obtained, the gain values of the first stage 201 and the second stage 202 are calibrated according to the same gain error estimate.
FIG. 4 shows a conventional process for estimating a gain error of a cyclic stage 414 of a cyclic ADC 400. Because N stages of the cyclic ADC 400 share a common physical circuit, the cyclic stage 414, the gain error correction module 420 needs to estimate only one gain error of the cyclic stage 414. The cyclic stage 414 first receives an analog input voltage Vin as the stage input signal I and generates a stage output value do, and a stage output signal R according to the analog input voltage Vin and a correction number P1 generated by the gain error correction module 420. The stage output signal R is then recursively fed back as the stage input signal I, and the cyclic stage 414 sequentially generates stage output values do2′, do3′, . . . doN′. A multiplexer 412 selects the analog input voltage Vin or the stage output signal R as the stage input signal of the cyclic stage 414 according to a clock signal. The gain error correction module 420 then determines a gain error ε by correlating the correction number P1 and the stage output values do2′, do3′, . . . doN′. After the gain error ε is obtained, the gain values of all N stages of the cyclic ADC 400 are calibrated according to the same gain error ε.
The gain error correction modules 220 in FIG. 2 must collect a great number of samples of the stage output values do2′˜doN′ to estimate the gain error ε of the first stage 201 and the second stage 202. Accordingly, the gain error correction modules 420 in FIG. 4 must collect a great number of samples of the stage output values do2′˜doN′ to estimate the gain error ε of the cyclic stage 414. The precision of the gain error estimate increases with the number of collected samples. If the number of collected samples is reduced, a low precision gain error estimate results. If the number of the collected samples is increased, the time required for collecting samples causes latency in gain error estimation. Thus, when multiple ADC stages share a common operational amplifier, a method for reducing time required for estimating a gain error of the multiple ADC stages without reducing precision of the gain error is desirable.